As the demand increases for cheaper, faster, lower power consuming integrated circuits, such as microprocessors, the transistor packing density of the integrated circuit must be similarly increased. To do so, the device dimensions of the integrated circuit are continually shrunk. Very large scale integration (VLSI) techniques have continually evolved to meet the increasing demand. All aspects of the integrated circuit must be scaled down to fully minimize the device dimensions. In addition to minimizing transistor dimensions, one must minimize the dimensions of the electrical interconnections which connect the transistors together on a microchip to form a complete circuit.
Currently, aluminum alloys are the most commonly used conductive materials for electrical interconnections in a VLSI integrated circuit. Aluminum and its alloys have been fully characterized for use as electrical interconnections, and much technology has been developed to aid in the formation of aluminum interconnections. Aluminum has very attractive features for use as an electrical interconnection, such as low electrical resistivity and strong adhesion to silicon dioxide. However, as VLSI dimensions reach into the deep-sub micron Ultra Large Scale Integration (ULSI) regime, the deficiencies of aluminum and its alloys become limiting factors in achieving superior performance. For example, as the width of electrical interconnections becomes narrower, even the low resistance of aluminum becomes non-negligible and begins to slow down the circuit. Additionally, with decreasing dimensions, design rules become increasingly restricted by aluminum interconnection reliability concerns such as electromigration, stress-induced void formation, hillock suppression, and current density limitations.
For these reasons, the microelectronics industry has recently migrated towards the investigation of more robust, more conductive metals for use in interconnection technology such as Copper (Cu). Cu is approximately 40% lower in resistivity than Al and is much more resistant to reliability problems such as electromigration. Unfortunately, Cu has been known to cause other reliability problems associated with the high rate of Cu diffusion through silicon substrates and dielectric films. One such problem is electrical shorting, wherein the Cu from one Cu interconnect line diffuses into an adjacent dielectric region, forming a conductive path to another Cu interconnect line. Another problem is transistor poisoning, wherein Cu diffuses into the underlying silicon substrate and causes Junction leakage along with reduced channel mobility in the transistor, thereby destroying the device. Therefore, to implement Cu as an interconnect material it has become necessary to develop methods for preventing Cu from diffusing through a semiconductor device.
One method for preventing copper diffusion through a semiconductor device is to employ a barrier between the copper interconnect and adjacent materials of the semiconductor device. FIG. 1 shows a cross section of a substrate 10 upon which a barrier 11 and a copper layer 12 are formed. Barrier 11 comprises a material which impedes the diffusion of copper from copper layer 12 into the underlying substrate 10. As shown, barrier 11 is not perfect. Barrier 11 comprises micro-defects 13 such as pinholes or voids in the film, and the barrier further comprises a number of grain boundaries, two of which ,14 and 15, are illustrated in FIG. 1. Micro-defect 13, along with grain boundaries 14 and 15, act as weak spots in the barrier, permitting copper from copper layer 12 to diffuse through to the underlying substrate 10. As shown, within micro-defect region 13 the copper of copper layer 12 comes into direct contact with substrate 10. Substrate 10 comprises silicon and silicon dioxide, through which copper will rapidly diffuse from the micro-defect in the barrier, particularly at elevated temperatures. Similarly, copper rapidly diffuses along grain boundaries of the barrier when subjected to elevated temperatures.
To better isolate copper layer 12 from the underlying substrate 10, the thickness of barrier 11 is simply increased. However, increasing the thickness of the barrier also increases the resistance of the resulting copper interconnect as illustrated in FIG. 2. FIG. 2 shows a cross section of a substrate 20 upon which an electrical interconnect comprising copper layer 23 and barrier 22 has been formed adjacent to dielectric material 21. As shown, the thickness of barrier layer 22 is large in comparison to the thickness of copper layer 23. It is necessary for barrier 22 to be thick enough to adequately prevent the diffusion of copper from copper layer 23 into either dielectric material 21 or substrate 20. Forming a thicker barrier reduces copper diffusion through micro-defects because the defects are more likely to be incorporated into the bulk of the barrier, thereby reducing diffusion paths through the defect. In addition, while a thicker barrier may still comprise grain boundaries leading from the upper to lower surface of the barrier, these boundaries are necessarily longer, thereby slowing copper diffusion and increasing the likelihood that a copper atom is blocked by, for example, a precipitate along the boundary. Because the grain boundaries are long, it would take a longer time for copper to diffuse through the length of these longer grain boundaries. While some copper atoms may successfully diffuse through these grain boundaries, it is expected that other reliability limitations of the integrated circuit will cause the device to fail by an alternate failure mechanism.
Note that as the thickness of barrier 22 increases, the volume which the highly conductive copper layer 23 occupies of the overall electrical interconnect decreases. Unfortunately, barrier 22 comprises materials which are at least 10 times more electrically resistive than copper, such as, for example, a dielectric such as silicon nitride. Therefore, increasing the barrier thickness while maintaining the overall width of the interconnect increases the total resistance of the electrical interconnect due to the reduction in volume that the low resistance copper material can occupy. The total width of the interconnect could be increased to counteract the increased resistance, but doing so would reduce the density of the integrated circuit.
Increasing the resistance of the electrical interconnect by increasing the thickness of barrier 22 defeats the advantages of employing copper as an interconnect material in the first place. As a result, the speed at which the integrated circuit operates is reduced. Thus, what is desired is a thin diffusion barrier which permits the low resistivity of copper or other interconnect material to be exploited in an electrical interconnect.